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Investigation and Implementation of Soft Error Mitigation and Detection for Belle II Trigger Modules

Investigation and Implementation of Soft Error Mitigation and Detection for Belle II Trigger Modules
Forschungsthema:Investigation and Implementation of Soft Error Mitigation and Detection for Belle II Trigger Modules
Typ:Bachelorarbeit
Datum:now
Betreuer:

Dipl.-Inform. Steffen Bähr

Background

 

The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, saving only relevant data. This approach solves the data transmission problem; however mechanisms implementing the identification have to be employed.

 

At the ITIV so called trigger mechanisms based on machine learning are developed for the Belle II experiment. These are implemented on FPGAs running in the so called electronics Hut (eHut). Since it is placed close to the detector in order to keep transmission delays small, it may be affected by radiation during runtime. This radiation might lead to soft errors, in which bits stored on the FPGA might flip, thus leading to false computation. Meanwhile the used trigger heavily relies on usage of learned constants, like weights of neurons in neural networks. Approaches for error detection and if possible error correction are desired and to be implemented, without having a high impact on the algorithm’s latency and performance.

 

Tasks of the Thesis

 

The main tasks of this thesis are the investigation and implementation of the impact of soft error mitigation techniques for FPGAs. Their impact and trade-offs are to be evaluated for Belle II CDC trigger modules like the neural network trigger, which is developed at ITIV.

 

  1. Familiarization phase
    1. Familiarization with soft error mitigation
    2. Orientation in design for FPGAs and the platforms used in Belle II
  2. Concept- and design phase
    1. Development of a soft error mitigation concept
    2. Evaluation of trade-offs
  3. Implementation phase
    1. Investigation on trigger modules
    2. Implementation of soft error mitigation approaches
  4. Documentation
    1. Creation of a  documentation covering the topics described above