In a Network-on-Chip architecture, tiles of processing elements communicate with each other over one integrated network. Tiles may consist of multiple homogeneous or heterogeneous computing cores, some of them being General Purpose Processors (GPPs).
Looking at one single tile, there have been many efforts to optimize the data processing performance of the processors inside. One approach is the Dynamic Intra-tile Cache Reallocation (DICAR) as depicted in the figure below, by which the cache architecture can be adapted to the workload of the processors.
In our case study, we predict that the DICAR may suffer from information leakage. This leakage is presumably caused by components of our DICAR which share the same peripherals or hardware resources. To develop a countermeasure, we need to estimate and mathematically model the channels in the DICAR.
- Learn the concept of DICAR in homogeneous GPPs
- Contrast the concept of DICAR with state-of-the-art concepts of dynamic or adaptive cache in the GPP architecture
- Estimate and create channel models of the DICAR
- Analyze and evaluate the models
- Student of electrical engineering or informatics
- Basic knowledge in computer architecture
- Eagerness to learn about caches and DICAR in GPPs
- Willingness to deal with mathematical models of channels in DICAR, especially using statistical modeling