english  | Home | Impressum | Datenschutz | KIT

Reconfiguration Management for Machine Learning Trigger Components on FPGAs for Belle II

Reconfiguration Management for Machine Learning Trigger Components on FPGAs for Belle II
Forschungsthema:FPGA Entwicklung
Typ:Bachelorarbeit
Datum:ab jetzt
Betreuer:

Dipl.-Inform. Steffen Bähr

Background

 

The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, while saving only relevant data. This approach solves the data transmission problem.

 

At the ITIV we are researching, implementing and integrating so called trigger mechanisms on FPGAs for Belle II. These are deciding over the readout of the detector during the collisions. A significant part of that system is using algorithms based on machine learning for example neural networks. These are typically trained and calibrated with a set of data representing the behavior of the particle accelerator at a certain point in time. To achieve optimal performance several sets are predefined and used, resulting in different calibrations of the algorithm. These calibrations have to be loaded dynamically in low latency during runtime depending on the current status of the collider. For that FPGAs offer several approaches for example dynamic partial reconfiguration. The task of this thesis is to investigate the possibilities.

 

Tasks of the Thesis

 

The main task of this thesis is the investigation of suitable reconfiguration management concepts for machine learning algorithms on FPGAs. These concepts shall be prototyped and evaluated based on Virtex Ultrascale FPGAs.

 

  1. Familiarization phase
    1. Familiarization with the machine learning algorithms on FPGAs used in Belle II
    2. Orientation in design for FPGAs and the platforms
  2. Concept- and design phase
    1. Concept of reconfiguration management for FPGAs
    2. Evaluation of the design choices based on Belle II
  3. Implementation phase
    1. Implementation and prototyping of the concept for the Belle II use case
    2. Evaluation and characterization of the concepts
  4. Documentation
    1. Creation of a  documentation covering the topics described above