A growing trend in designing embedded systems is that multiple applications with different requirements share the same hardware platform to improve resource utilization and cost. These platforms are moving towards multi/many core architectures and use Network-on-Chip (NoC) for communication. With the increasing number of cores on such platforms, the complexity of the interconnect is increasing and it will become a limiting factor for performance. Efficiency and performance can be improved if the NoC is able to adapt to the requirements of different applications while still meeting the constraints. Designing a flexible NoC architecture which can be managed at runtime is a key challenge.
An existing NoC shall be made adaptable by changing the network infrastructure at varying levels of granularity. Some possible examples of such adaptations are: designing flexible topologies, routers and algorithms. The NoC will be designed using Hardware Description Languages, implemented and tested on a multi-FPGA system. The exact task will be decided after consultation with the supervisor.
- Knowledge of hardware description languages like VHDL or Verilog.
- Experience with hardware design and with using design tools for Xilinx FPGAs is an advantage.
- Motivation and interest in solving technical problems independently.