The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, while saving only relevant data. This approach solves the data transmission problem.
At the ITIV we are researching, implementing and integrating so called trigger mechanisms for the Belle II experiment that decide over the readout of the detector. One such trigger mechanism is a Hough transform based estimation of particle tracks passing through the detector. In this approach all possible curves that might have caused a sensor of the detector to be active are calculated, afterwards the most probable curve is calculated by combining all active sensors. However at each time several curve candidates are existing, but only one has to be selected for representation of a particle that passed through the detector. The selection is done by performing a clustering and afterwards center of gravity estimation on a multi-dimensional Hough map. This clustering has to be implemented on FPGAs to conform with the real-time requirements that are present for latency and throughput.
Tasks of the Thesis
The main task of this master thesis is the evaluation and implementation of clustering algorithms on FPGAs. The algorithm is to be designed for an n-dimensional discrete space of cells. As a use case a 3-dimensional hough map is to be implemented and tested on a Virtex Ultrascale FPGA
- Familiarization phase
- Familiarization with clustering algorithms and their implementation on FPGAs
- Orientation in design for FPGAs and the platforms used in Belle II
- Concept- and design phase
- Concept for a low-latency n-dimensional clustering algorithm for FPGAs
- Evaluation of the design choices for the FPGA
- Implementation phase
- Implementation and Integration of the concept into the Belle II use case
- Evaluation and characterization of different implementation variations
- Creation of a documentation covering the topics described above