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Evaluierung neuronaler Netze unter Nutzung des Hybrid Memory Cube Speichers

Evaluierung neuronaler Netze unter Nutzung des Hybrid Memory Cube Speichers
Forschungsthema:Machine Learning auf FPGAs / Speicherinfrastruktur
Typ:Bachelorthesis
Datum:ab jetzt
Betreuer:

Dipl. Inform Steffen Bähr 

Evaluierung neuronaler Netze unter Nutzung des Hybrid Memory Cube Speichers

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Belle II Detektor

Background

The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, saving only relevant data. This approach solves the data transmission problem; however mechanisms implementing the identification have to be employed.

At the ITIV we are researching, implementing and integrating so called trigger mechanisms for the Belle II experiment. They allow to separate interesting from uninteresting detector data. As this separation has to be done early on to reduce the amount of data to be saved, such mechanisms have to be implemented on FPGAs. Together with our colleagues from physics we showed that neural networks are a suitable approach for a trigger mechanism in this context. However much more has to be done in order for it to be used in the upcoming experiment.

 

Tasks of the Thesis

The usage of neural networks has to evaluated for the hybrid memory cube, which is a new memory architecture using 3D-stacked memory instead of the commonly used approaches. An architecture for loading and storing of network weights has the be developed first. It's capabilities are to be demonstrated on a FPGA based platform that is provided  micron.

Required skills

VHDL, FPGA, C knowledge