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HW/SW Co-Simulation von Trigger Submodulen der zentralen Driftkammer des Belle II Teilchendetektor-Experiments

HW/SW Co-Simulation von Trigger Submodulen der zentralen Driftkammer des Belle II Teilchendetektor-Experiments
Forschungsthema:HW/SW Co-Simulation / FPGAs
Datum:ab jetzt

Dipl. Inform Steffen Bähr   



The upcoming Belle II particle collider experiment is the most modern particle detector experiment in the world. It will target a world record Luminosity, which corresponds to the number of particle collisions over time. The resulting amount of data to be saved for later analysis of the experiment is simply too huge to get across the data transmission lines. Fortunately a huge chunk of data is produced by effects that are not important for the experiment, as they don’t result in new knowledge. Identifying this data early on allows discarding uninteresting data, saving only relevant data. This approach solves the data transmission problem; however mechanisms implementing the identification have to be employed.


At the ITIV we are researching, implementing and integrating so called trigger mechanisms for the Belle II experiment. They allow to separate interesting from uninteresting detector data. As this separation has to be done early on to reduce the amount of data to be saved, such mechanisms have to be implemented on FPGAs. Meanwhile the functionality of the implemented algorithms has to be validated and kept consistent with the Belle II trigger simulation framework, which is used to determine the effectiveness of a developed algorithm.


Tasks of the Thesis


In main task of this bachelor thesis is to develop a concept and framework for a HW/SW Co-Simulation integrated with the Belle II trigger simulation. For this the already present VHDL representations of the FPGA implementation are to be integrated with the physics simulation of the detector using the Vivado High-Level Synthesis tool.


  1. Familiarization phase
    1. Familiarization with HW/SW Co-Simulation and Vivado HLS simulation
    2. Orientation in design for FPGAs and the Belle II simulation framework
  2. Concept- and design phase
    1. Development of a simulation and integration concept
    2. Evaluation of the design choices
  3. Implementation phase
    1. Implementation and Integration of the developed concept
    2. Evaluation and characterization of different variations
  4. Documentation
    1. Creation of a  documentation covering the topics described above