Self assembled nano architectures experience a high degree of defects due to their stochastic nature. Even in the VLSI circuits the shrinking feature size causes nano scale devices to have unprecedented level of defects. Therefore fault tolerance is very important in the future nano scale designs. In the main work we take care about the reliability of every local area in the whole architecture. Due to the reconfigurability every local area consist of very small building blocks. In every local area the failure rate in a special cycle time is measured and based on it the whole reliability situation of the area is computed. In the test method every building block is ruled as either Block Under Test (BUT), Test Pattern Generator (TPG) or Output Response Analyzer (ORA) to check its neighbors or to be checked by its neighbors for probable failures. What is expected to be done in this work, is development of the testing method in every cycle using a hardware description language like VHDL. You simulate a local area and count the number of failures in every cycle for small building blocks.
A basic knowledge about the hardware description languages. You will surely improve your abilities during the work.