According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. We strongly
believe that in future architectures it become more important assessing the fault tolerance techniques. Having an estimation of system fault tolerance can ensure critical applications working properly. In this work we search for reliability estimation of the reconfigurable architectures. Using the reliabilities which are assigned to different areas of architecture we try to find the best places for applications in architecture. We have a redundant application running to guarantee system correctness. In the case of a failure which is detected by our arbiter we go to the Detail Test phase (DT) and estimate the reliability of the faulty area.
In this work we need to evaluate the system which is a simulation of our nano scale architecture. We use Matlab to do this simulation. In the next step we try to implement the simulated results using hardware description languages like VHDL.
- Experience in programming