The fundamental limits of current CMOS process for future design technology have directed attentions toward nano technology architectures. These architectures bring opportunities in the future design and have advantages and disadvantages based on their dense nature. The study of defect and fault tolerance in Nano-technologies is one of the major subjects in this era. Because of the high defect rate comes from density, the well-known fault detection ways have to be adapted to use in these systems.

Due to the regularity imposed by the fabrication process of nano architectures, it is unlikely that complex circuits can be constructed. Reconfigurability is therefore an integral part of nano-architectures as the circuit will be programmed into the desired functionality at post-fabrication. In this work we want to show how to use the test and fault tolerance methods in FPGAs and reconfigurable architectures to recognize the defects in future nano architectures.

 

A deep research about the test and fault tolerant methods in FPGAs is expected.

These methods will further be used in offline defect recognition in nano architectures.

We use the idea behind and then extend it in the cases of high defect rates.

 

 

A good knowledge about the fault tolerance theme and FPGAs as well